Prof. Jack Dongarra
University Distinguished Professor, Department of Electrical Engineering & Computer Science, University of Tennessee Distinguished Research Staff, Oak Ridge National Laboratory, USA
Jack Dongarra holds an appointment at the University of Tennessee, Oak Ridge National Laboratory, and the University of Manchester. He specializes in numerical algorithms in linear algebra, parallel computing, use of advanced-computer architectures, programming methodology, and tools for parallel computers. He was awarded the IEEE Sid Fernbach Award in 2004 and in 2008 he was the recipient of the first IEEE Medal of Excellence in Scalable Computing; in 2010 he was the first recipient of the SIAM Special Interest Group on Supercomputing’s award for Career Achievement. He is a Fellow of the AAAS, ACM, IEEE, and SIAM and a member of the National Academy of Engineering.
Prof. Thomas Sterling
Professor of Informatics and Computing at the Indiana University (IU) School of Informatics and Computing, Chief Scientist of the IU Center for Research in Extreme Scale Technologies (CREST), USA
Dr. Thomas Sterling holds the position of Professor of Informatics and Computing at the Indiana University (IU) School of Informatics and Computing as well as serves as Chief Scientist of the IU Center for Research in Extreme Scale Technologies (CREST). Since receiving his Ph.D from MIT in 1984 as a Hertz Fellow Dr. Sterling has engaged in applied research in fields associated with parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the "father of Beowulf" for his pioneering research in commodity/Linux cluster computing. He was awarded the Gordon Bell Prize in 1997 with his collaborators for this work. He was the PI of the HTMT Project sponsored by NSF, DARPA, NSA, and NASA to explore advanced technologies and their implication for high-end computer system architectures. Other research projects included the DARPA DIVA PIM architecture project with USC-ISI, the Cray Cascade Petaflops architecture project sponsored by the DARPA HPCS Program, and the Gilgamesh high-density computing project at NASA JPL. Thomas Sterling is currently engaged in research associated with the innovative ParalleX execution model for extreme scale computing to establish the foundation principles guiding co-design for the development of future generation Exascale computing systems. ParalleX is currently the conceptual centerpiece of the XPRESS project as part of the DOE X-stack program and has been demonstrated in proof-of-concept in the HPX-5 runtime system software. Dr. Sterling is the co-author of six books and holds six patents. He was the recipient of the 2013 Vanguard Award and is a Fellow of the AAAS.
Prof. Ruibo Wang
National University of Defense Technology, China
Ruibo Wang is a professor at National University of Defense Technology. He is the deputy director of the Institution of High Performance Computer and now holds an appointment as the leading designer of next-gen Tianhe Software Stack. He has been working on operating system and fault tolerant management for Tianhe-1 and Tianhe-2 supercomputers. His current research interests include high performance computer architecture and implementation technologies, transactional memory, and kernel performance measurement. He received a Bachelor of Engineering (2003) and a Ph.D (2011) in Computer Science and Technology from the National University of Defense Technology.
Prof. Mateo Valero Cortés
Director of Barcelona Supercomputing Center (BSC), Spain
Mateo Valero is a professor at Technical University of Catalonia, UPC, and the Director of the Barcelona Supercomputing Center. His research focuses on high performance architectures. He has published over 700 papers, has served in the organization of more than 300 international conferences and he has given more than 500 invited talks.
Dr. Valero has been honoured with several awards. Among them, the Eckert-Mauchly Award 2007 by the IEEE and ACM; Seymour Cray Award 2015 by IEEE; Charles Babbage 2017 by IEEE; Harry Goode Award 2009 by IEEE: ACM Distinguished Service Award 2012; Euro-Par Achievement Award 2015; the Spanish National Julio Rey Pastor award, in recognition of research in Mathematics; the Spanish National Award “Leonardo Torres Quevedo” that recognizes research in engineering; the “King Jaime I” in basic research given by Generalitat Valenciana; the Research Award by the Catalan Foundation for Research and Innovation and the “Aragón Award” 2008 given by the Government of Aragón. "Hall of the Fame" member of the ICT European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon,November 2008); Honoured with Creu de Sant Jordi 2016 by Generalitat de Catalunya. It is the highest recognition granted by the Government. Honoured with “Condecoración de la Orden Mexicana del Águila Azteca” 2018, highest recognition granted by the Mexican Government
In 1998 he won a “Favourite Son” Award of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named their Public College after him.
He is Honorary Doctorate by 9 Universities. He is a fellow of IEEE and ACM and is and Intel Distinguished Research Fellow. He is member of 8 academies.
Prof. Dr. Dr. Thomas Lippert
Jülich Supercomputing Center, Germany
Thomas Lippert received his diploma in Theoretical Physics in 1987 from the University of Würzburg. He completed Ph.D. theses in theoretical physics at Wuppertal University on simulations of lattice quantum chromodynamics and at Groningen University in the field of parallel computing with systolic algorithms. He is director of the Jülich Supercomputing Centre at Forschungzentrum Jülich, member of the board of directors of the John von Neumann Institute for Computing (NIC), and he holds the chair for Computational Theoretical Physics at the University of Wuppertal. He is the coordinator of the European Exascale-Projects DEEP, DEEP-ER and DEEP-EST, he is a member of the scientific and infrastructure board of the human brain project, and since July 2018, he is chair of the Council of the Partnership for Advanced Computing in Europe (PRACE). Thomas' research interests include lattice gauge theories, quantum computing, numerical and parallel algorithms, and modular supercomputing.
Prof. Dr. Thomas Ludwig
German Climate Computing Centre & Universität Hamburg, Germany
Thomas Ludwig received his doctoral degree and the German habilitation degree at the Technische Universität München, where he conducted research on HPC from 1988 to 2001. From 2001 to 2009 he had a chair for parallel computing at the Universität Heidelberg. 2009 he moved to Hamburg. He is now director of the German Climate Computing Center (DKRZ) and professor at the Universität Hamburg. His research activity is in the fields of high volume data storage, energy efficiency, and performance analysis concepts and tools for parallel systems. At DKRZ Prof. Ludwig takes the responsibility for accomplishing its mission: to provide high performance computing platforms, sophisticated and high capacity data management, and superior service for premium climate science.
Prof. Michael Resch
University of Stuttgart, Germany. Director of the HPC Center Stuttgart, Director of the Institute for HPC, Full professorship for HPC, Dean of the faculty for Energy- Process- and Biotechnology
The focus of research of Prof. Dr.-Ing. Dr. h.c. Dr. h.c. Hon. Prof. Michael M. Resch is currently on the application of supercomputers in engineering and industrial research as well as the scientific theory of simulation. He is leading projects in the fields of High Performance Computing, Cloud computing, visualization, scalable parallel algorithms, and philosophy of simulation. At the center of his research is the applicability of mathematical methods and computer science to real world problems. Prof. Resch has a more than 25 year track record in high performance computing. In 2007 his activities in supercomputing were honored by an invitation to be an invited plenary keynote speaker at SC’07 in Reno, USA - the most important supercomputing conference worldwide. He was winner of the HPC Challenge in 2003 at SC’03 at Phoenix, USA and leader of the group that won the US NSF award for real distributed supercomputing in 1999. Prof. Resch is a Principal Investigator (PI) in the national cluster of excellence for “Simulation Technology (SimTech)” funded by the German DFG as part of the German Initiative for Excellence in Research. As a PI, Prof. Resch takes responsibility for the research area on “Hybrid High-Performance Computing Systems and Simulation Software Engineering”. Within the cluster of excellence Prof. Resch collaborates intensively with sociologists and philosopher on the foundations of simulation and their impact in society and politics.
Prof. Hiroaki Kobayashi
Professor of Graduate School of Information Sciences, Tohoku University, Japan
Hiroaki Kobayashi received his Ph.D in Information Engineering from Tohoku University in 1988. Since then, he has been a faculty member of School of Engineering and Graduate School of Information Sciences, Tohoku University. His research interests are in high-performance, low-power processor architectures, 3D chip architectures, parallel and distributed computing, supercomputing systems and their applications. He was Visiting Associate Professor of Stanford University in 1995, 1997, and 2000 to work with Professor Michael J. Flynn on low-power processor design. In 2008-2016, he was Director of Cyberscience Center of Tohoku University, which is one of 7 national supercomputer centers in Japan. He has been involved in many supercomputing projects such as “feasible study of a future HPC system for memory-intensive applications,” which was conducted under the national program for exascale computing by Ministry of Education, Culture, Sports, Science and Technology of Japan. In this project, he has designed a novel vector system with 3D die-stacking technology with NEC. He is a member of Science Council of Japan. He has been the chair of Organizing Committee of COOL Chips, IEEE Symposium on Low-Power and High-Speed Chips since 2011.